首页> 外国专利> TRENCH TYPE DMOS TRANSISTOR MANUFACTURED BY RELATIVELY SMALL NUMBER OF MASKING PROCESSES AND HAVING THICK OXIDE LAYER IN DISTAL REGION, AND ITS MANUFACTURING METHOD

TRENCH TYPE DMOS TRANSISTOR MANUFACTURED BY RELATIVELY SMALL NUMBER OF MASKING PROCESSES AND HAVING THICK OXIDE LAYER IN DISTAL REGION, AND ITS MANUFACTURING METHOD

机译:相对较小数量的制造过程和远端区域具有厚氧化层的沟槽型DMOS晶体管及其制造方法

摘要

PPROBLEM TO BE SOLVED: To provide a DMOS transistor which is manufactured in the relatively small number of masking processes and improves a process controllability and a stability of a breakdown voltage, and its manufacturing method. PSOLUTION: The trench type DMOS transistor is manufactured by using seven masking processes, and one of the processes defines a p+ type deep main body region and forms an active region of the transistor in which its mask is formed in a LOCOS process. Another masking process defines an insulating oxide layer of a distal region thicker than the active region of the transistor, whereby a contamination of a substrate in a production process is reduced and the process controllability can be improved. Further, a field effect distribution is improved by the thick field oxide layer in the distal region, and an electron avalanche yield voltage can be stably expected. PCOPYRIGHT: (C)2008,JPO&INPIT
机译:

要解决的问题:提供一种DMOS晶体管及其制造方法,该DMOS晶体管以相对少的掩模工艺制造,并且提高了工艺可控性和击穿电压的稳定性。

解决方案:沟槽型DMOS晶体管是通过使用七个掩模工艺制造的,其中一个工艺定义了p +型深主体区域,并形成了晶体管的有源区,在该有源区中,其掩模通过LOCOS工艺形成。另一掩膜工艺限定了远侧区域的绝缘氧化物层,该远侧区域的厚度比晶体管的有源区域厚,从而减少了生产工艺中的基板污染并且可以提高工艺可控性。此外,通过在远侧区域中的厚场氧化物层改善了场效应分布,并且可以稳定地预期电子雪崩屈服电压。

版权:(C)2008,日本特许厅&INPIT

著录项

  • 公开/公告号JP2007281515A

    专利类型

  • 公开/公告日2007-10-25

    原文格式PDF

  • 申请/专利权人 SILICONIX INC;

    申请/专利号JP20070168352

  • 申请日2007-06-27

  • 分类号H01L21/336;H01L29/78;H01L29/06;

  • 国家 JP

  • 入库时间 2022-08-21 21:15:33

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