Architecture for hardware-assisted context switching between register groups dedicated to time-critical or non-time critical tasks without saving state

摘要

In one embodiment of the present invention, a processing system for processing information efficiently and cost-effectively by switching between execution of time-critical and non-time-critical tasks includes a processing unit. The processing system further includes a first register group coupled to the processing unit and including a first set of registers, the processing unit reading the status of the first set of registers to execute time-critical tasks. The processing system further includes a second register group coupled to the processing unit and including a second set of registers, the second register group for updating the status of the second set of registers, the processing unit reading the status of the second set of registers to execute the non-time-critical tasks by avoiding saving the status of the first set of registers, wherein the processing unit switches between executing time-critical tasks and non-time-critical tasks efficiently and cost-effectively by avoiding saving status of the first or second set of registers.