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Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores
Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores
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机译:普遍采用时钟门控处理器内核的基于架构级别吞吐量的功率建模方法和装置
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摘要
A method for estimating power dissipated by processor core processing a workload includes analyzing a reference test case to generate a reference workload characteristic, analyzing an actual workload to generate an actual workload characteristic, performing a power analysis for the reference test case to establish a reference power dissipation value and estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value.
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