Programmable clock synchronizer for computer system, configures synchronization controllers operating in different clock domain responsive to sync pulse that is sampled in clock domains

摘要

A configuration interface configures synchronization controllers operating in different clock domain responsive to a sync pulse that is sampled in the clock domains, to compensate for variable skew factor and variable latency factor associated with clock signal. The controllers output control signals to the synchronizers to control data transfer between the bus and core clock domain logic blocks.