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SOI STRUCTURE SINGLE EVENT TOLERANCE INVERTER, NAND ELEMENT, NOR ELEMENT, SEMICONDUCTOR MEMORY ELEMENT, AND DATA LATCH CIRCUIT
SOI STRUCTURE SINGLE EVENT TOLERANCE INVERTER, NAND ELEMENT, NOR ELEMENT, SEMICONDUCTOR MEMORY ELEMENT, AND DATA LATCH CIRCUIT
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机译:SOI结构单事件容差逆变器,NAND元,NOR元,半导体存储器元和数据锁存电路
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摘要
Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (3P1, 3P2; 3N1, 3N2). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (3I).
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