HIGH SPEED VITERBI DECODING METHOD WITH ANALOG IMPLEMENTATION AND CIRCULAR CONNECTION OF ITS TRELLIS DIAGRAM

摘要

The present invention relates to a fast Viterbi decoding method by the analog implementation of the trellis diagram and the cyclical connection. The present invention determines the decoding result value of 1 or 0 based on whether the output value of the output stage is changed as a result of the electrical signal flow blocking of the decoding stage. A method of decoding the output signal before and after the flow interruption is decoded, or the reference signal is propagated while the electric signal flow to specific branches is blocked in advance, and then the difference is compared with a predetermined threshold value. It is characterized by decoding using any one of a method of decoding using whether or not.;According to the present invention, not only is the decoding speed fast, but also the path memory for decoding is unnecessary, and the power consumption is very small.;Viterbi decoder, trellis diagram, trigger signal, two-dimensional parallel processing structure