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Integrated circuit - arrangement and method for the determination of the parasitic ohmic resistance of at least the feed line at least one memory cell of an integrated circuit - arrangement
Integrated circuit - arrangement and method for the determination of the parasitic ohmic resistance of at least the feed line at least one memory cell of an integrated circuit - arrangement
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机译:集成电路-用于确定至少馈电线的集成电路的至少一个存储单元的寄生欧姆电阻的装置和方法-装置
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摘要
An integrated circuit - arrangement has at least one electronic component as well as at least one hand, with the electronic component and coupled with the monolithically integrated resistor - judging circuit for determining the parasitic ohmic resistance of at least the feed line to the at least one electronic component.
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