Input circuit for use in memory device, has adjusting circuit adjusting operation of receiver such that duty ratio of data signal converges towards fifty percentage duty ratio, and detecting circuit detecting offset voltage

摘要

The circuit has a receiver circuit (440) generating a data signal based on a pair of differential data signals (DQ, DQN). An adjusting circuit (470) adjusts the operation of the receiver circuit such that duty ratio of data signal converges towards fifty percentage duty ratio. A detecting circuit (460) detects an offset voltage between the differential data signals, by comparing the generated data signal to a reference voltage (V ref), where the detecting circuit generates two voltages representing the detected offset voltage based on the comparison. Independent claims are also included for the following: (1) a method of reducing influences of offset in an input circuit; (2) a memory system comprising a memory controller; and (3) a memory device comprising an input circuit.