Embedded testing circuit for testing e.g. static random access memory, has embedded data generation circuit generating internal test data pattern in response to external test data pattern, where external test data pattern is switchable

摘要

The circuit has an embedded address generation circuit for generating an internal address in response to an external address, where the internal address has an internal row selection address and an internal column selection address. An embedded data generation circuit generates an internal test data pattern in response to an external test data pattern, where the external test data pattern for accessing a memory cell array (11) through a port is switchable such that it is inverted by an inverter when the array is accessed through another port. Independent claims are also included for the following: (1) a testing system for testing dual port memories, comprising an external tester (2) a method for testing a dual port memory.