Ternary coded decimal comparator circuit based on ternary and quaternary logic, by logically combining signals in binary manner and providing results as ternary value

摘要

The comparator uses ground 0, +5 V, -5 V, and high resistance state 0 to represent the logical numbers 0,1,2 and 3. The modules carrying the ternary signals are connected to a bus via only two lines. The two lines are converted back into three lines in an input logic unit (9) within a signal processing module. Although these signals are ternary compatible, they are logically combined in a binary manner, and at the output of the module the result is provided as a ternary value via an END-gate (17), which can be processed again in only two lines, representing the three ternary digits for encoding a TCD digit.