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cmos image sensor and method for driving a cmos image sensor with increased dynamic range

机译:cmos图像传感器和用于驱动动态范围增加的cmos图像传感器的方法

摘要

The imager comprises a set of pixels each comprising a photodiode (PD) as a photodetecting element generating charge carriers in proportion to illumination, a capacitor (C1) as a storage element which can be coupled or decoupled from the photodiode in order to store at a memory node (B) a signal measuring the charge carriers generated by the photodiode, and five MOS transistors (M1 to M5). At least one transistor (M1,M3) is connected in series with the photodiode, directly or via a coupling transistor (M2), and is configured so to function at least partially with weak inversion so that in exposition phase the pixel has a logarithmic response for illumination levels higher than a predetermined level. The transistor (M2) couples the photodiode (PD) in reverse bias to the capacitor (C1), that connects the nodes (A) and (B). The transistor (M3) initializes the memory node (B) to a determined voltage. The drains of transistors (M1,M3) are connected to different supply voltages, that is the voltages (VBIAS) and (VDD), respectively, where the voltage (VBIAS) is higher than the voltage (VDD). The transistor (M4) is a source-follower transistor, and the transistor (M5) is a row-selection transistor which ensures the voltage transfer to an output bus common to all pixels in a column. The imager also comprises means for switching the gate voltage of at least one transistor (M1,M3) between the voltages (V1) and (V2), where the voltage (V1) is higher than the supply voltage (VDD) plus a threshold voltage (VTH), and the voltage (V2) is lower than the supply voltage (VDD) plus a threshold voltage (VSS) plus the threshold voltage (VTH). The photodiode (PD) is formed in an n-type well, and the transistors (M1 to M5) are n-MOS transistors. The storage element (C1) is formed as a capacitor protected from light by a metallic layer. A method is claimed for operating the imager and comprises the step of exposition consisting in connecting the transistor (M1) as a resistance, the step of storage consisting in decoupling the photodiode from the capacitor, and the step of reading the stored signal measure; or the steps of initialization, exposition, storage and reading. At the reading step a voltage is applied to the gate of the transistor (M1) so that the charge carriers generated by the photodiode (PD) are drained via that transistor.
机译:成像器包括一组像素,每个像素包括一个光电二极管(PD)作为光电检测元件,与照度成比例地产生电荷载流子;一个电容器(C1)作为存储元件,可以与光电二极管耦合或解耦以便存储在一个在存储节点(B)中,测量由光电二极管产生的电荷载流子的信号,以及五个MOS晶体管(M1至M5)。至少一个晶体管(M1,M3)直接或通过耦合晶体管(M2)与光电二极管串联,并且被配置为至少部分地具有弱反转功能,从而在曝光阶段像素具有对数响应对于高于预定水平的照明水平。晶体管(M2)将反向偏置的光电二极管(PD)耦合到电容器(C1),电容器C1连接节点(A)和(B)。晶体管(M3)将存储节点(B)初始化为确定的电压。晶体管(M1,M3)的漏极分别连接到不同的电源电压,即电压(VBIAS)和(VDD),其中电压(VBIAS)高于电压(VDD)。晶体管(M4)是源极跟随器晶体管,而晶体管(M5)是行选择晶体管,其确保电压传输到列中所有像素共用的输出总线。成像器还包括用于在电压(V1)和(V2)之间切换至少一个晶体管(M1,M3)的栅极电压的装置,其中电压(V1)高于电源电压(VDD)加阈值电压(VTH),并且电压(V2)低于电源电压(VDD)加阈值电压(VSS)加阈值电压(VTH)。光电二极管(PD)形成在n型阱中,并且晶体管(M1至M5)是n-MOS晶体管。存储元件(C1)形成为通过金属层保护免受光的电容器。要求保护一种操作成像器的方法,该方法包括以下步骤:曝光,将晶体管(M1)连接为电阻;存储步骤,将光电二极管与电容器去耦;以及读取存储的信号量的步骤;或初始化,展示,存储和读取的步骤。在读取步骤中,将电压施加到晶体管(M1)的栅极,以便由光电二极管(PD)生成的电荷载流子通过该晶体管排出。

著录项

  • 公开/公告号DE60218674D1

    专利类型

  • 公开/公告日2007-04-19

    原文格式PDF

  • 申请/专利权人 ASULAB S.A.;

    申请/专利号DE2002618674T

  • 发明设计人 DOERING ELKO;GRUPP JOACHIM;

    申请日2002-05-31

  • 分类号H01L27/146;H04N5/355;H04N5/3745;

  • 国家 DE

  • 入库时间 2022-08-21 20:27:51

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