Circuit placement optimization problem processing method and circuit arrangement optimization problem processing computer-readable recording medium for recording the program

摘要

The present invention relates to a technique relating to a method of processing a layout optimization problem. In connection with an element layout optimization problem in which it is requested to optimally arrange a plurality of elements within a space of two or more dimension, a first algorithm executing step is carried out. In this step, when information concerning the state of initial layout of the plurality of elements is available, a genetic algorithm is executed, thereby reducing non-uniformity in density of the plurality of elements staying in the initial layout. Subsequently, a second algorithm executing step is executed. In this step, when there are input data regarding the state of layout unbalance reduction halfway stage of the plurality of elements after reduction of non-uniformity in density in the first algorithm executing step, a local layout unbalance reducing algorithm is executed, thereby further reducing non-uniformity in density of the plurality of elements staying in the layout unbalance reduction halfway stage. As a result, the layout optimization problem of optimally arranging the plurality of elements in a space is processed. In this way, an element layout optimization problem of large scale is also processed.