首页>
外国专利>
Regular routing for deep sub-micron chip design
Regular routing for deep sub-micron chip design
展开▼
机译:用于深亚微米芯片设计的常规布线
展开▼
页面导航
摘要
著录项
相似文献
摘要
A method of routing an interconnect metal layer of an integrated circuit, wherein single-width nets are replicated and routed in parallel to reduce the total resistance on the net; wide wires are decomposed into a several single-width wires routed in parallel to improve uniformity of metal interconnect routing and therefore manufacturability of metal interconnect layers. The decomposition step is performed during a preliminary wire route after initial physical placement. Access to pin shapes is ensured through a branching and a recombination of the parallel single-width wires. Separate wire segments are rejoined at the source and sink of the net. The parallel wire segments do not change the logic behavior of the circuit.
展开▼