Low-speed DLL employing a digital phase interpolator based upon a high-speed clock

摘要

A low-speed delay locked loop (DLL) facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected. The phase chosen is that which eliminates any difference in the phases of the 156 MHz clock that clocks the data transmitted to the ASIC domain and the clock that is used in the ASIC domain to latch the data. Thus, the interpolator takes advantage of the availability of the high-speed clock to generate a sufficient number of phases for a low speed DLL.