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Optimizing IC clock structures by minimizing clock uncertainty
Optimizing IC clock structures by minimizing clock uncertainty
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机译:通过最小化时钟不确定性来优化IC时钟结构
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摘要
A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.
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