首页> 外国专利> METHOD OF FABRICATING REDUCED SUBTHRESHOLD LEAKAGE CURRENT SUBMICRON NFET'S WITH HIGH III/V RATIO MATERIAL

METHOD OF FABRICATING REDUCED SUBTHRESHOLD LEAKAGE CURRENT SUBMICRON NFET'S WITH HIGH III/V RATIO MATERIAL

机译:高III / V比例材料的亚阈值泄漏电流亚微米NFET减小方法

摘要

A method of fabricating an enhancement mode semiconductor device (50) comprises providing a compound semiconductor substrate (12), epitaxially growing on the substrate a first portion (14) of a buffer (11), the first portion (14) including gallium arsenide (GaAs), growing a second portion (15) of the buffer, the second portion (15) including a high V/III ratio and high aluminum (Al) mole fraction aluminum gallium arsenide (AlGaAs), and epitaxially growing a stack (10) of compound semiconductor layers on the buffer (11). An enhancement mode semiconductor device is then formed in the stack.
机译:一种制造增强模式半导体器件(50)的方法,包括提供化合物半导体衬底(12),在该衬底上外延生长缓冲器(11)的第一部分(14),该第一部分(14)包括砷化镓( GaAs),生长缓冲液的第二部分(15),第二部分(15)包含高V / III比和高铝(Al)摩尔分数的砷化铝镓铝(AlGaAs),并外延生长堆叠(10)缓冲层(11)上的化合物半导体层的数量。然后在堆叠中形成增强模式半导体器件。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号