Shared component clock protrction for multicore DSP device

摘要

A digital signal processing chip having a multiple processor cores with corresponding processor subsystems, a shared component, and a clock tree, is disclosed herein. A clock tree (131) distributes clock signals to the processor cores and the shared component. The clock tree (131) can be configured to disable one or more of the processor cores and the shared component by blocking the corresponding clock signal. This may advantageously conserve power. However, the clock tree (131) is configured to preserve the clock signal to the shared component as long as at least one of the processor cores has not disabled the shared component. That is, to block the clock signal to the shared component, each of the processor cores must disable the shared component. The shared component may, for example, be a shared program memory or an arbiter for an external input/output port. The clock tree may include a register and a series of clock gates (306, 308, 310, 312, 314, 316, 318, 320, 322, 324). Each of the clock gates (306, 308, 310, 312, 314, 316, 318, 320) blocks the clock signal (INT. CLK) when a gate signal is de-asserted. The gate signals (326) are generated from enablement bits in the register. The clock signal for the shared component is gated by a clock gate (312, 322; 314, 324) that blocks the clock signal only if each of the processor cores have disabled their enablement bit for the shared component. IMAGE