Controller for fast, deterministic and fault-tolerant bus system-bus, is designed to prevent issuing of wake-up signal for preset time period without prior reception of synchronization signal

摘要

The controller has a central processing unit with a state machine i.e. program code, which defines different software conditions. The controller is designed to initiate delivery of a synchronization signal to a flexray(RTM: Fast, deterministic and fault-tolerant bus system) bus after activation by an incoming wake-up signal without prior reception of the signal over/through the bus. The controller is designed to prevent issuing of another wake-up signal for a preset time period without prior reception of the synchronization signal.