FRAMEWORK FOR RESULTS INTERPRETATION AND GUIDED REFINEMENT OF SPECIFICATIONS FOR PLC LOGIC VERIFICATION

摘要

A system and method for interpreting formal verification results of PLC logic code used to control a manufacturing process, or other automated process, where the interpretation process does not require highly skilled technicians having significant experience in computer and mathematical algorithms. The verification process includes providing a verification results summary to check the compliance of the code with respect to the specifications. The verification results summary is analyzed and categorized to determine whether violations or errors are found in the results. The results can be depicted by assertion trees if a direct assertion between the PLC logic and the specifications can be provided. Alternatively, the results can be depicted by a reduced ladder logic if a direct assertion between the PLC logic and the specifications cannot be provided and a simulation is required. The specification refinement suggestions will be provided if the critical variable for violations is identified.