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Tri-level test mode terminal in limited terminal environment
Tri-level test mode terminal in limited terminal environment
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机译:受限终端环境中的三级测试模式终端
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摘要
A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input level. The technique substantially reduces or eliminates false detections of the test mode and substantially reduces or eliminates falsely enabling other (e.g., functional) mode(s) of the integrated circuit.
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