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Critical path estimating program, estimating apparatus, estimating method, and integrated circuit designing program

机译:关键路径估计程序,估计装置,估计方法和集成电路设计程序

摘要

A computer-readable recording medium on which is recorded a program, which is used by a computer for estimating a critical path among a plurality of paths given as paths within an integrated circuit, for causing the computer to execute a process, the process comprising receiving from a memory inputs of a logic description for the integrated circuit, and the plurality of given paths, obtaining a path evaluation value, which represents a delay of a path, for each of the given paths, and prioritizing the paths according to evaluation values, and estimating a path having a large evaluation value as the critical path.
机译:一种在其上记录有程序的计算机可读记录介质,该程序由计算机用于估计作为集成电路内的路径而给出的多个路径中的关键路径,以使该计算机执行处理,该处理包括:从集成电路的逻辑描述的存储器输入和多个给定路径中,获得每个给定路径的代表路径延迟的路径评估值,并根据评估值对路径进行优先级排序,估计值为较大的路径作为关键路径。

著录项

  • 公开/公告号US7493580B2

    专利类型

  • 公开/公告日2009-02-17

    原文格式PDF

  • 申请/专利权人 KEISUKE HORITA;

    申请/专利号US20060468900

  • 发明设计人 KEISUKE HORITA;

    申请日2006-08-31

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 19:30:00

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