Disclosed is a mixed mode parallel processor system in which the appreciable increase of circuit scale is avoided and lowering of performance in SIMD processing does not occur. N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (= N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the PEs, where PS, operate as an instruction cache. The remaining memories operate as data memories or as data cache memories. One out of S sets of general-purpose registers, inherently belonging to the PEs, directly operates as a general register group for the PU. Out of the remaining S-1 sets, T set or a required number of sets, where T S-1, are used as storage registers that store tags of the instruction cache.
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