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SYSTEM FOR SCHEDULING BASED ON HW/SW CO-DESIGN AND METHOD THEREFOR

机译:基于硬件/软件协同设计的调度系统及其方法

摘要

A scheduling system and method based on hardware/software integration design are provided to make dynamic scheduling possible by using a hardware scheduler without artificial scheduling for a hardware task and a software task, thereby performing hardware/software tasks parallely at an instruction level. An instruction patch module(20) patches instruction from an instruction cache memory(10). An instruction queue module(40) stores the instruction which the instruction patch module patches from the instruction cache memory. An instruction dispatch module(30) reads the instruction stored in the instruction queue module. A memory related instruction buffer(50) stores a result enforcing the memory related instructions and re-arranges the result according to an original execution sequence. A register related instruction buffer(60) stores general-purpose instruction related information or primitive instruction related information among the instructions which the instruction dispatch module reads, stores a result enforcing a general-purpose instruction or a primitive instruction, and re-arranges the result according to an original execution sequence.
机译:提供了一种基于硬件/软件集成设计的调度系统和方法,以通过使用硬件调度程序来进行动态调度,而无需对硬件任务和软件任务进行人工调度,从而在指令级并行执行硬件/软件任务。指令修补模块(20)修补来自指令高速缓冲存储器(10)的指令。指令队列模块(40)存储指令补丁模块从指令高速缓冲存储器中修补的指令。指令分配模块(30)读取存储在指令队列模块中的指令。与存储器有关的指令缓冲器(50)存储执行与存储器有关的指令的结果,并根据原始执行顺序重新排列结果。寄存器相关指令缓冲器(60)在指令分配模块读取的指令中存储通用指令相关信息或原始指令相关信息,存储执行通用指令或原始指令的结果,并重新排列结果根据原始执行顺序。

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