首页> 外国专利> METHOD OF FABRICATING A SEMICONDUCTOR DEVICE REDUCING A THERMAL BUDGET ON IMPURITY REGIONS OF A PERIPHERAL CIRCUIT REGION

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE REDUCING A THERMAL BUDGET ON IMPURITY REGIONS OF A PERIPHERAL CIRCUIT REGION

机译:在外围电路区域的杂质区域上制造半导体器件以减少热预算的方法

摘要

A method for manufacturing a semiconductor device for reducing a thermal budget to impurity regions of a peripheral circuit region is provided to improve characteristics of the semiconductor device by forming a peripheral transistor after performing a high-temperature process. A substrate(110) including a cell array region and a peripheral circuit region is prepared. The cell array region includes a cell activation region(112c). The peripheral circuit region includes peripheral activation regions(112a,112b). A cell gate pattern(126a) and a peripheral gate pattern(126b) are formed across the cell activation region and the peripheral activation region. A plurality of first cell impurity regions(130c) are formed in the cell activation regions of both sides of the cell gate pattern. A cell bottom interlayer dielectric(136) and a peripheral insulating layer are formed on the substrate in order to cover the cell array region and the peripheral circuit region, respectively. A plurality of cell conductive pads(144c) are formed through the cell bottom interlayer dielectric in order to be electrically connected with the first cell impurity regions. The peripheral insulating layer is removed to expose the peripheral activation regions of both sides of the peripheral gate pattern.
机译:提供一种用于制造用于减少对外围电路区域的杂质区域的热预算的半导体器件的方法,以通过在执行高温工艺之后形成外围晶体管来改善半导体器件的特性。制备包括单元阵列区域和外围电路区域的基板(110)。细胞阵列区域包括细胞激活区域(112c)。外围电路区域包括外围激活区域(112a,112b)。跨单元激活区域和外围激活区域形成单元栅图案(126a)和外围栅极图案(126b)。在单元栅极图案的两侧的单元激活区中形成多个第一单元杂质区(130c)。单元底部层间电介质(136)和外围绝缘层形成在基板上,以便分别覆盖单元阵列区域和外围电路区域。贯穿单元底部层间电介质形成多个单元导电垫(144c),以便与第一单元杂质区电连接。去除外围绝缘层以暴露外围栅极图案的两侧的外围激活区域。

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