Use of a plurality of voltage controlled delay lines for the precise alignment and work cycle control of the data output of a german democratic republic - memory device

摘要

A dll - circuit uses a rising edges - the delay locked loop, in order to the rising edge of the output data to align with the system clock, and a trailing edges - the delay locked loop, in order to align the trailing edge of the output data. The dll - circuit uses the falling edge of the input clock pulse is not, in order to obtain a reference for the trailing edges - the delay locked loop to provide. The dll - circuit uses the leading edge of a first incremented (a buffered version of the input clock), in order to align the leading edge of the output data. An additional delay locked loop is used in order to produce a precise second reference clock, which, in order to exactly half a period of the first is delayed incremented, in order to align the trailing edge of the output data. A variation in the working cycle of the input clock pulse or of the input clock buffer has no effect on the work cycle of the output data.