Electrolysis cell layout, to be used by the design manner of the semiconductor integrated circuit device and the semiconductor integrated circuit and the design of the semiconductor production mannered

摘要

PPROBLEM TO BE SOLVED: To provide a cell layout which can suppress change of a metal layer to the minimum, and to provide a semiconductor integrated circuit device using the same, a method of designing a semiconductor integrated circuit, and a method of manufacturing semiconductor of the semiconductor integrated circuit. PSOLUTION: A cell layout is used for designing a semiconductor integrated circuit. The cell layout relates to a standard cell or a macro cell having an input cell terminal 4a, an output cell terminal 4b, and a plurality of cell units (Delay 1-4) arranged in series. On a metal layer of the cell unit, input dummy metal wiring 1a capable of carrying out mutual connection between adjacent cell units and output dummy metal wiring 1b set for connection in the same manner as with the input dummy metal interconnect line 1a traversing the metal layer and an input terminal 11 and an output terminal 12 provided between the input dummy metal wiring 1a and the output dummy metal wiring 1b are arranged. PCOPYRIGHT: (C)2005,JPO&NCIPI