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BUMP WITH MULTIPLE VIAS FOR SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF, AND SEMICONDUCTOR PACKAGE UTILIZING THE SAME
BUMP WITH MULTIPLE VIAS FOR SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF, AND SEMICONDUCTOR PACKAGE UTILIZING THE SAME
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机译:半导体封装用多个焊口的凹凸及其制造方法,以及利用相同结构的半导体封装
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摘要
A bump for a semiconductor package forms a polymer layer having multiple vias on an electrode pad above a semiconductor chip to increase an electrical contact area between the electrode pad and a metal bump. Further, the bump forms a polymer layer having multiple vias on a redistribution electrode pad to increase a surface area of an electrode interconnection. The multiple vias increase electrical and mechanical contact areas, thereby preventing current crowding and improving joint reliability. The bump for a semiconductor package may further comprise a stress relaxation layer at the lower portion of the bump.
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