Using a delay clock to optimize the timing margin of sequential logic

摘要

A circuit including a first stage register that operates in response to a first clock having a period T_CYCLE, a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register that operates in response to the second clock, combinational logic coupled between the first register output and the second register input, and a third register having an input coupled to the second register output. The programmable delay is selected: (1) to have a positive value if the signal delay between the first and second registers exceeds T_CYCLE, and (2) such that the signal delay between the second and third registers is less than T_CYCLE minus the programmable delay. Additional delayed clocks generated in response to the second clock signal can be used to operate additional second stage registers, thereby staggering the outputs of these second stage registers within T_CYCLE.