首页> 外国专利> PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications

PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications

机译:基于PC的计算系统,具有集成的图形子系统,以对图形应用程序透明的方式支持来自相同或不同供应商的多个不同图形处理单元(GPUS)上的并行图形处理操作

摘要

PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUs) supplied from the same or different vendors. The graphics subsystem include a graphics controller hub (GCH) chip located on a CPU bus, and having Multi-Pipeline Core Logic (MP-CL) circuitry including a routing unit and a control unit. The plurality of different GPUs are interfaced with the GCH chip. Each different GPU supports a GPU-driven pipeline core having a frame buffer (FB) for storing a fragment of pixel data. The GPU-driven pipeline cores are arranged in a parallel architecture and operated according to a parallelization mode of operation, so that said GPU-driven pipeline cores process data in a parallel manner. In one illustrative embodiment, the different GPUs are located (i) within an integrated graphics device (IGD) within the GCH chip, and also (ii) on one or more external GPU-based graphics cards from the same or different vendors. In another illustrative embodiment, the different GPUs are located on a plurality of external GPU-based graphics cards from different vendors. Diverse illustrative embodiments are disclosed.
机译:基于PC的计算系统,具有集成的图形子系统,该子系统支持从相同或不同供应商提供的多个不同图形处理单元(GPU)上的并行图形处理操作。图形子系统包括位于CPU总线上的图形控制器集线器(GCH)芯片,并具有多管道核心逻辑(MP-CL)电路,该电路包括路由单元和控制单元。多个不同的GPU与GCH芯片接口。每个不同的GPU都支持GPU驱动的管线核心,该核心具有用于存储像素数据片段的帧缓冲区(FB)。 GPU驱动的管线核心以并行架构布置并且根据并行化操作模式进行操作,从而所述GPU驱动的管线核心以并行方式处理数据。在一个说明性实施例中,不同的GPU位于(i)在GCH芯片内的集成图形设备(IGD)内,并且(ii)位于来自相同或不同供应商的一个或多个基于外部GPU的图形卡上。在另一个说明性实施例中,不同的GPU位于来自不同供应商的多个基于外部GPU的图形卡上。公开了各种说明性实施例。

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