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TFT array panel with improved connection to test lines and with the addition of auxiliary test lines commonly connected to each other through respective conductive layers which connect test lines to respective gate or data lines
TFT array panel with improved connection to test lines and with the addition of auxiliary test lines commonly connected to each other through respective conductive layers which connect test lines to respective gate or data lines
A thin film transistor (TFT) array panel with improved contact between the display signal lines and test lines is presented. The TFT array panel includes: gate lines and data lines intersecting each other, switching elements connected to the gate lines and the data lines, and at least one test line disposed near end portions of the gate lines or the data lines. An insulating layer covers the gate lines, the data lines and the switching elements and has first contact holes exposing the end portions of the gate lines or the data lines and second contact holes exposing the test lines. Auxiliary test lines are formed on the insulating layer and commonly connected to conductive layers, wherein the conductive layers connect at least one test line to the gate lines or the data lines via the first and the second contact holes.
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