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Parallelized hardware architecture to compute different sizes of DFT
Parallelized hardware architecture to compute different sizes of DFT
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机译:并行硬件架构可计算不同大小的DFT
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摘要
To speed up the computation the invention proposes to use two computation cores in parallel to compute a DFT. Data are dispatched between the two cores according to the even and odd lines of the PFA Ruritanian mapping matrix. Separate storage means are used for each core and means are provided to exchange data between the two separate storage means between the radix computation steps.
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