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VOLATILE MEMORY INCLUDING GATE DIELECTRIC HAVING CHARGE TRAP, AND METHOD OF MANUFACTURING THE SAME

机译:包含门介电电荷陷阱的挥发性记忆体及其制造方法

摘要

PROBLEM TO BE SOLVED: To provide a volatile memory that has a desired threshold voltage value although relatively lowering the doping concentration of a channel ion implantation region.SOLUTION: The volatile memory includes: a cell transistor having a lower gate dielectric, an intermediate gate dielectric for charge trapping, and an upper gate dielectric, all laminated in order as a gate dielectric; and a transistor for logic, having a single layer of an oxide film as a gate dielectric.
机译:解决的问题:提供一种具有所需阈值电压值的易失性存储器,尽管相对降低了沟道离子注入区的掺杂浓度。解决方案:该易失性存储器包括:具有较低栅极电介质的单元晶体管,中间栅极电介质用于电荷俘获和上部栅极电介质,它们全部按顺序层叠为栅极电介质;以及用于逻辑的晶体管,具有单层氧化膜作为栅极电介质。

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