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The compliment which

机译:夸奖

摘要

PPROBLEM TO BE SOLVED: To provide a level converter which is capable of determining an initial value of a latch circuit and has excellent symmetry in rising/falling characteristics of an output signal. PSOLUTION: MOS transistors Tp3, Tp4 for initial value setting are inserted and connected between nodes N1, N2 that become output terminals of first and second inverters 32, 33 constituting a latch circuit 31 of a shift circuit 12 and transistors Tp1, Tp2. A gate of the MOS transistor Tp3 is then connected to a ground and a gate of the MOS transistor Tp4 is connected to an initial value setting circuit 34. The initial value setting circuit 34 controls a gate potential of the MOS transistor Tp4 to an intermediate potential between a second high potential power source VDE and the ground when the second high potential power source VDE is below a predetermined level, and controls the gate potential to a ground level so as to turn on the MOS transistor Tp4 when the second high potential power source VDE is above the predetermined level. PCOPYRIGHT: (C)2008,JPO&INPIT
机译:

要解决的问题:提供一种电平转换器,该电平转换器能够确定锁存电路的初始值,并且在输出信号的上升/下降特性中具有优异的对称性。

解决方案:用于初始值设置的MOS晶体管Tp3,Tp4插入并连接在节点N1,N2之间,节点N1,N2成为构成移位电路12的锁存电路31的第一和第二反相器32、33的输出端,并且。然后,将MOS晶体管Tp3的栅极接地,并且将MOS晶体管Tp4的栅极连接至初始值设置电路34。初始值设置电路34将MOS晶体管Tp4的栅极电势控制为中间电势。当第二高电位电源VDE低于预定电平时,在第二高电位电源VDE和地之间导通,并且在第二高电位电源时将栅极电势控制到地电平以导通MOS晶体管Tp4。 VDE高于预定水平。

版权:(C)2008,日本特许厅&INPIT

著录项

  • 公开/公告号JP5012208B2

    专利类型

  • 公开/公告日2012-08-29

    原文格式PDF

  • 申请/专利权人 富士通セミコンダクター株式会社;

    申请/专利号JP20070135675

  • 发明设计人 古藤 友彦;

    申请日2007-05-22

  • 分类号H03K19/0185;

  • 国家 JP

  • 入库时间 2022-08-21 17:38:38

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