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Method, logic device and system for calculating circuit jitter, and method, logic device and system for synthesizing circuit clock tree
Method, logic device and system for calculating circuit jitter, and method, logic device and system for synthesizing circuit clock tree
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机译:用于计算电路抖动的方法,逻辑设备和系统,以及用于合成电路时钟树的方法,逻辑设备和系统
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摘要
In one embodiment, a method for computing jitter in a clock tree includes dividing a clock tree into a plurality of stages and computing jitter in one or more of the stages according to a model of at least a portion of a circuit associated with the clock tree. The model includes a representation of each source of jitter in the circuit. The method also includes, to compute jitter associated with a path or a pair of paths in the clock tree, statistically combining the jitter in each of the stages of the path or the pair of paths in the clock tree with each other. In one embodiment, to efficiently compute jitter and to achieve zero clock skew, a method synthesizes a symmetrical clock tree of a circuit in which corresponding stages in all paths from a root of the clock tree to sinks of the clock tree exhibit approximate electrical equivalence to each other.
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