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APPARATUS AND METHOD FOR MODELING COARSE STEPSIZE DELAY ELEMENT AND DELAY LOCKED LOOP USING SAME
APPARATUS AND METHOD FOR MODELING COARSE STEPSIZE DELAY ELEMENT AND DELAY LOCKED LOOP USING SAME
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机译:使用相同模型对粗步长延迟元素和延迟锁定环进行建模的装置和方法
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摘要
A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.
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