COURSE LOCK DETECTOR HAVING NO A STUCK PROBLEM AND A HARMONIC LOCK AT HIGH SPEED

摘要

PURPOSE: A course lock detector is provided to eliminate a stuck problem and a harmonic lock at high speed using an even/odd sampling method.;CONSTITUTION: A divider(705) outputs a clock signal having the half frequency of a signal by receiving a reference clock of PH[0]. The divider receives the half frequency clock signal of the reference clock as a third input signal through each frequency detection cell. A third frequency detection cell(730) receives the output signal of a first frequency detection cell(710), QA[1], as a second input signal. The inputted signal is transmitted to a flip flop(734) through an AND operation with PH[9] which is received as a first input signal from an AND gate(732). A signal outputted through the flip flop, QA[3], is used as the second input signal for a fifth frequency detection cell(750).;COPYRIGHT KIPO 2013