A method and bus architecture for sending data in a bus architecture from a slave device to master pathways via a bus

摘要

A method and bus architecture for sending data in a bus architecture from a slave device (405) to master pathways (e.g. connecting master devices (401a,401b, 401c, 401d) by a bus) the architecture comprising a buffer (e.g. optimiser 411) for buffering data from at least one slave device, wherein the clock rate of the bus is higher than the clock rate of each master pathway. The method includes the steps of; maintaining in the buffer a data queue for each master pathway for the date received from the slave device, selecting a data packet at the front of each master pathway queue in the buffer in a round robin manner and sending the the selected data packet to the master pathway to which it is directed. The method addresses problems associated with bottlenecks caused by different clock rates. There may be an arbiter (409) between the optimiser (411) and the master devices (401).