MACRO TIMING ANALYSIS DEVICE, MACRO BOUNDARY PATH TIMING ANALYSIS METHOD AND MACRO BOUNDARY PATH TIMING ANALYSIS PROGRAM

摘要

A macro timing analysis device comprises a netlist merging unit which merges a layout-implemented top netlist obtained by executing clock path distribution and layout processing with respect to a top netlist with a lower-order hierarchy as a macro and a layout-implemented macro netlist obtained by cutting out a circuit in the macro from the layout-implemented top netlist to generate a merging-implemented macro netlist including description of a clock path outside the macro and description of a macro boundary path which are clock paths related to the macro, and a timing analysis unit which analyzes a timing of the macro boundary path by using the merging-implemented macro netlist.