Verification device of semiconductor integrated circuit, verification method of semiconductor integrated circuit, and computer readable medium storing verification program of semiconductor integrated circuit

摘要

According to one embodiment, a verification device of semiconductor integrated circuit includes an assertion based verification unit, a logic generating unit, a signal restriction generating unit, and an estimation unit. The assertion based verification unit performs assertion based verification of the circuit description based on the assertion description, and generates pass information when the operation of the signal described in the assertion description conforming to a preliminary condition is observed in the circuit description, or generates failure information when the operation of the signal is not observed in the circuit description. The logic generating unit extracts a signal corresponding to the failure information from the assertion description, and generates an input/output logic of the circuit description from the extracted signal. The signal restriction generating unit generates a signal restriction based on the input/output logic. The estimating unit evaluates the validity of the signal restriction.