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Data error check circuit, data error check method, data transmission method using data error check function, semiconductor memory apparatus and memory system using data error check function
Data error check circuit, data error check method, data transmission method using data error check function, semiconductor memory apparatus and memory system using data error check function
Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column direction and a row direction of data groups to be transmitted through a plurality of data input/output terminals in a read operation and output the error check signals together with the data groups, and a memory controller configured to control data read/write operations of the semiconductor memory apparatus, generate error check signals by performing error check in a column direction and a row direction of data groups to be transmitted in a write operation, and provide the error check signals to the semiconductor memory apparatus together with the data groups.
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