DEVICE UNDER TEST TEST METHOD SHARING AN OUTPUT CHANNEL APPLIED TO AN AUTOMATIC TEST EQUIPMENT, DEVICE UNDER TEST AND A SEMICONDUCTOR DEVICE TEST SYSTEM THEREBY

摘要

PURPOSE: A DUT test method, a DUT and a semiconductor device test system are provided to reduce the number of IO pins of a DUT required for a test.;CONSTITUTION: A DUT(100) includes five IO pins, a chip level tap controller(10), a plurality of cores(20-1-20-M), a star controller(30) and a three phase buffer(40). Four IO pins receive a test input data signal, a test mode input signal, a clock signal and a reset signal and one output pin outputs test output data. The plurality of cores executes input signals applied from the input pins and individually output test output data. The chip level tap controller transmits a test command, test output data and an output enable signal based on the input signals. The star controllers calculates linear regression shift of the test input data signal and the test mode input signal in response to the clock signal and the reset signal. The star controller selects a test core and a test method in the plurality of cores based on a calculated first control value, performs a test and selects an output target DUT to output test output data based on a calculated second control value or a master bit. The three phase buffer outputs the test output data of the output target DUT based on the output enable signal.;COPYRIGHT KIPO 2013