首页> 外国专利> Improved split-gate non-volatile flash memory cell, array, and fabrication method having a floating gate, a control gate, a select gate, and an erase gate with an overhang on the floating gate

Improved split-gate non-volatile flash memory cell, array, and fabrication method having a floating gate, a control gate, a select gate, and an erase gate with an overhang on the floating gate

机译:改进的分裂栅非易失性闪存单元,阵列和制造方法,其具有浮栅,控制栅,选择栅和在浮栅上具有突出端的擦除栅

摘要

An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
机译:在具有第一导电类型的基本单晶衬底中制造改进的分裂栅非易失性存储单元,该衬底具有第二导电类型的第一区域,第二导电类型的第二区域以及在第一区域之间的沟道区域。衬底中的第二区域。该单元具有在沟道区的一部分上方的选择栅,在沟道区的另一部分上方的浮栅,在浮栅上方的控制栅以及与浮栅相邻的擦除栅。擦除栅极具有在浮置栅极上方延伸的突出端。悬垂尺寸与浮置栅极和擦除栅极之间的垂直间隔的尺寸之比在大约1.0至2.5之间,这提高了擦除效率。

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