首页> 外国专利> Method and system for concurrently locating systematic bits and parity bits in physical channel memory to increase HARQ processing speed in 3GPP CPC system

Method and system for concurrently locating systematic bits and parity bits in physical channel memory to increase HARQ processing speed in 3GPP CPC system

机译:在3GPP CPC系统中同时定位物理信道存储器中系统位和奇偶校验位以提高HARQ处理速度的方法和系统

摘要

A UE receives a HS-PDSCH transmission from a base station and concurrently performs rate matching on systematic bits and parity bits (parity 1 bits, parity 2 bits) of the received HS-PDSCH transmission. The systematic bits and parity bits are buffered in a CPC circular buffer to support HARQ processing in a HS-SCCH-less operation of the base station. Memory locations are computed for the systematic bits and the parity bits according to corresponding transmission parameters such as, for example, redundancy version, number of systematic bits and/or number of physical channels. The systematic bits and the parity bits are stored in the corresponding computed memory locations of the CPC circular buffer. At least a portion of the stored systematic bits and parity bits are concurrently generated based on corresponding transmission parameters from the CPC circular buffer per request to support concurrent rate matching on systematic bits and parity bits.
机译:UE从基站接收HS-PDSCH传输,并且同时对接收到的HS的系统比特和奇偶校验比特(奇偶校验 1 比特,奇偶校验 2 比特)执行速率匹配。 -PDSCH传输。系统位和奇偶校验位在CPC循环缓冲区中进行缓冲,以支持基站的无HS-SCCH的操作中的HARQ处理。根据相应的传输参数,例如冗余版本,系统位数和/或物理通道数,为系统位和奇偶校验位计算存储位置。系统位和奇偶校验位存储在CPC循环缓冲区的相应计算存储位置中。每个请求基于来自CPC循环缓冲区的相应传输参数并发地生成至少一部分存储的系统位和奇偶校验位,以支持系统位和奇偶校验位的并发速率匹配。

著录项

  • 公开/公告号US8817711B2

    专利类型

  • 公开/公告日2014-08-26

    原文格式PDF

  • 申请/专利权人 SIMON BAKER;

    申请/专利号US20100768486

  • 发明设计人 SIMON BAKER;

    申请日2010-04-27

  • 分类号H04J1/16;

  • 国家 US

  • 入库时间 2022-08-21 16:04:00

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