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System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design

机译:指导由物理实现数据定义的电路设计的补救性转换,以减少电路设计中检测到的时序违规所需的物理校正的系统和方法

摘要

A system and method are provided for pessimism reduction of a timing database provided for optimization of a circuit design. Pessimism is reduced through generation of a hybrid graph-based static timing analysis (GBA) and path-based static timing analysis (PBA STA) database. PBA is selectively performed on the most critical GBA identified timing violations with the goal of reducing erroneous pessimism in operational timing characteristics passed on to the physical implementation corrective optimizer module to thereby reduce unnecessary fixing and transformations upon the circuit design to correspondingly reduce design time, temporary storage space, needed processing power for timing closure and to result in a finished operable and tangible circuit device with reduced area, power requirements, and decreased cost.
机译:提供了一种用于减少时序数据库的悲观性的系统和方法,该时序数据库被提供用于电路设计的优化。通过生成基于混合图的静态时序分析(GBA)和基于路径的静态时序分析(PBA STA)数据库,可以减少悲观情绪。 PBA在最关键的GBA识别时序违规上有选择地执行,目的是减少传递给物理实现校正优化器模块的操作时序特性中的错误悲观情绪,从而减少不必要的电路固定和转换,从而相应地减少了设计时间(临时)存储空间,定时关闭所需的处理能力,以及导致完成的可操作且有形的电路设备,其具有减小的面积,功率要求和降低的成本。

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