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Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy
Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy
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机译:用于在电路设计期间根据布局对寄生建模的技术以及使用变化精度的模式进行寄生感知的电路设计的技术
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摘要
A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.
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