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FMA UNIT FOR UTILIZATION IN MODEL COMPUTATION UNIT FOR PURELY HARDWARE-BASED COMPUTING OF FUNCTION MODEL

机译:基于FMA的纯硬件模型计算单元中的模型计算单元

摘要

PROBLEM TO BE SOLVED: To provide an FMA (floating point multiply and add operation, e.g., fused multiply-add operation) unit for carrying out an arithmetic operation in a model computation unit of a control unit.SOLUTION: The FMA unit, for carrying out an arithmetic operation in a model computation unit of a control unit, is configured to process input of two multiplicands and one augend in the form of floating point values, and provide a computation result of such processing as an output variable in the form of a floating point value. The FMA unit is designed to carry out a multiplication and a subsequent addition, the bit resolutions of the inputs corresponding to the multiplicands being lower than the bit resolution of the input corresponding to the augend and the bit resolution of the output variable.
机译:要解决的问题:提供一个FMA(浮点乘法和加法运算,例如,融合乘法加法运算)单元,以便在控制单元的模型计算单元中进行算术运算。解决方案:FMA单元,用于执行在控制单元的模型计算单元中进行算术运算,被配置为以浮点值的形式处理两个被乘数和一个整数的输入,并以a的形式提供该处理的计算结果作为输出变量浮点值。 FMA单元被设计为执行乘法和随后的加法,对应于被乘数的输入的位分辨率低于对应于被乘数的输入的位分辨率和输出变量的位分辨率。

著录项

  • 公开/公告号JP2014229318A

    专利类型

  • 公开/公告日2014-12-08

    原文格式PDF

  • 申请/专利权人 ROBERT BOSCH GMBH;

    申请/专利号JP20140106814

  • 发明设计人 FISHER WOLFGANG;ANDRE GUNTORO;

    申请日2014-05-23

  • 分类号G06F7/76;

  • 国家 JP

  • 入库时间 2022-08-21 15:30:14

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