OPTIMIZING IC DESIGN USING RETIMING AND PRESENTING DESIGN SIMULATION RESULTS AS RESCHEDULING OPTIMIZATION

摘要

A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of paths. Each path includes a plurality of nodes that represent IC components including clocked elements and computational elements. The method optimizes the timing performance of the IC design by retiming a set of paths. The retiming includes skewing clock signals to a set of clocked elements by more than a clock period without changing the position of any clocked element relative to the position of the computational elements in the set of paths. The method performs simulation on the optimized IC design and provides the result of the simulation as a clock skew scheduling of the IC design instead of retiming of the IC design.