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Systems and methods for a floating-point multiplication and accumulation unit using a partial-product multiplier in digital signal processors
Systems and methods for a floating-point multiplication and accumulation unit using a partial-product multiplier in digital signal processors
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机译:用于数字信号处理器中使用部分积乘法器的浮点乘法和累加单元的系统和方法
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摘要
An embodiment of an apparatus performs a floating-point multiply-add process on a first multiplicand, a second multiplicand, and an addend. A leading 0 bit is added to a mantissa of the first multiplicand to form an expanded first mantissa, and a partial-product multiplication is performed on the expanded first mantissa and a mantissa of the second multiplicand to produce partial-product sum and a partial-product carry mantissas. Leading bits of the partial-product sum and carry mantissas are changed to 0 bits if they are both 1 bits, and the partial-product sum and the partial-product carry are shifted right according to an exponent difference of a product of the first multiplicand and the second multiplicand. Otherwise both the partial-product sum and carry mantissas are arithmetically shifted right according to the exponent difference. The first and second multiplicands and the addend can be complex numbers.
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