Design space exploration of optimal k-cycle transient fault tolerant datapath based on multi-objective power-performance tradeoff

摘要

The present invention discloses a system (apparatus) and method for design space exploration of an optimal single or multi cycle (k-cycle) transient fault detectable and /or error correctable data path which indicates design space exploration method producing design solutions with ability of k-cycle transient fault detection and/or error correction and generation of an optimal k-cycle transient fault detectable and /or fault correctable datapath that minimizes user specified power and delay (or performance) constraint, by detecting transient faults using a double/ dual modular redundancy (DMR)and/or correcting them using a double/ dual modular redundancy (DMR) with recovery circuit. Further, the present invention enables to achieve high reliability of the systems by considering fault tolerance (detectability and/or correctability) as design metric (or constraint) besides power and execution delay during multi-objective design space exploration (DSE) in high level synthesis (HLS).