Design and performance analysis of discrete wavelet transform based image fusion and compression for micro air vehicle applications

摘要

Micro air vehicles that are of less than 15 centimeter in size and weigh less than 20 grams need to navigate autonomously and avoid obstacles. The onboard image sensors acquire data from remote locations and transmit to the base stations, occupying more memory and require large bandwidth. Data collected by swarm of MAVs at the base station need to be fused to obtain relevant information. In this work, Discrete Wavelet Transform that forms the primary block in image compression, fusion and registration is designed and implemented on VLSI platform optimizing speed, area and power. Wavelet filters such as Biorthogonal and Daubechies are analyzed for their performances in reconstruction of image after compression and fusion. Image size and type of image being processed impact PSNR which is a measure of algorithm. DWT results are compared with DCT results considering Daubechies Wavelets, an improvement of 32% in terms of PSNR are achieved in image compression using DWT. In order to improve performances of DWT computation such as area, speed and power dissipation modified lifting based DWT is designed using pipelining architecture. The pipelined lifting DWT architecture is implemented on Xilinx FPGA. The proposed architecture reduces slice utilization by 31%, power is reduced by 48% and operating frequency by 73%. Further the pipelined lifting architecture is optimized for power dissipation by modifying the architecture incorporating low power techniques such as clock gating, power gating, device sizing, logic restricting, balanced gate delay, glitch reduction and voltage & frequency scaling techniques. The power dissipation is reduced by 20% and operating frequency is increased by 4% at the cost of additional hardware. 3D image compression using 3D-DWT algorithm is designed and implemented on VLSI platform using modified systolic array architecture. The systolic array architecture optimizes area by 31%, power dissipation by 3% and operating frequency by 30% for ID-DWT. The ID-DWT architecture is extended in realizing 3D-DWT architecture. The 3D-DWT architecture realized using systolic array logic reduces are by 41%, increases operating frequency by 35% and reduces power by 1.5% as compared with conventional DWT architecture. DWT based image fusion algorithm is designed and implemented on Virtex II pro FPGA considering 10,000 pixels of image (100 x 100 image size) which is loaded onto internal memory of FPGA. The novel image fusion algorithm operates at 307 MHz, consuming power of less than 0.21 W and occupying 436 slices. The DWT algorithm developed can be used as a digital Intellectual Property (IP).